Emulate radiation-induced faults on real FPGAs.
SK-RAFT injects targeted bit flips into AMD-Xilinx devices over JTAG, so you can see how your design behaves under radiation, right from your own desk. In hours, not months.
The circuit, and the data it runs on.
An FPGA has two kinds of memory. Many tools only flip bits in the configuration memory. SK-RAFT flips bits in both, while your design runs.
Holds the design. A flip here changes the circuit itself.
The state your design holds from one clock to the next.
The data your design stores while it runs.
Distributed memory built from the device's look-up tables.
Spend your test time on the bits that can break you.
In a typical design, only a fraction of the configuration bits are essential. SK-RAFT can limit a campaign to what does matter, which saves a lot of test time:
Essential bits only: the bits that can break your design.
One area of the chip: a single Pblock.
One component of your design.
Access. Map. Configure and run.
Everything goes through JTAG. No hardware modification.
- 01 · Access
SK-RAFT connects to the device over JTAG.
It connects to the device's JTAG controller, the standard debug interface on every FPGA board. No modification and no extra hardware. That connection is the entry point to everything inside the device.
- 02 · Map
It maps the device from your design files.
SK-RAFT parses your design files and builds a complete model of the device. From then on it knows exactly where to reach, whether it is an essential configuration bit or an application memory bit in flip-flops, BRAM or LUTRAM, down to every region, frame and bit location.
- 03 · Configure & run
You define the fault campaign.
Choose what to inject, where, and how many times, or replay a campaign recorded at a radiation facility. SK-RAFT handles execution, observation and logging, automatically, repeatedly and deterministically.
A campaign in a few lines of Python.
Control SK-RAFT from Python API scripts. Other languages can be supported through its gRPC interface. Over the same USB cable (JTAG), SK-RAFT also sends inputs to your design and reads its outputs, so you see the effect of each bit flip at once.
The illustrative script on the right connects to the board, programs it with your design files and starts a random fault-injection session limited to essential bits.
if __name__ == "__main__": dut = skClient.SkRaftFpga("127.0.0.1", 50052) fiSession = FpgaFiSession( fi_type=RANDOM, # Random or Exhaustive duration=200, # Duration (ms) correction_time=50, time_between_faults=10, sbu_percent=0.30, mbu_percent=0.40, mcu_percent=0.30, essential=True, correct=True ) dut.establish_connection() dut.fpga_autoconnect() dut.fpga_set_bit_file_path("/path/to/design.bit") dut.fpga_set_ebd_file_path("/path/to/design.ebd") dut.fpga_set_ll_file_path("/path/to/design.ll") dut.fpga_program() dut.fpga_fault_injection(fiSession)
How often a bit flip becomes a failure.
A campaign measures your design's architectural vulnerability factor (AVF): the share of bit flips that reach an observable failure. AVF belongs to the design, not the silicon, so it can be combined with a device's per-bit sensitivity to estimate failure rate and availability on the device and orbit you are targeting.
A typical reliability engagement with our team delivers:
Test plan
What will be injected, where, and how often.
Fault-injection report
What was injected and how your design responded.
Dependability report
An estimate of failure rate and availability for your target device and orbit.
AMD-Xilinx today. Versal next.
- 7-SeriesSupported
- Zynq-7000Supported
- UltraScale+Supported
- Zynq UltraScale+Supported
- VersalComing next
Working with another device? Tell us about it.